1. Field of the Invention
This invention is related to the field of processors and, more particularly, to interfacing processors with other components in a system.
2. Description of the Related Art
Processors are typically included in systems with other components and are configured to communicate with the other components via an interconnect on which the processor is designed to communicate. The other components may be directly connected to the interconnect, or may be indirectly connected through other components. For example, many systems include an input/output (I/O) bridge connecting I/O components to the interface.
Typically, the processor includes an interface unit designed to communicate on the interconnect on behalf of the processor core. The processor core generates requests to be transmitted on the interconnect, such as read and write requests to satisfy load and store operations and instruction fetch requests. Additionally, most processors implement caches to store recently fetched instructions/data, and implement cache coherency to ensure coherent access by processors and other components even though cached (and possible modified) copies of blocks of memory exist. Such processors receive coherency related requests from the interconnect (e.g. snoop requests to determine the state of a cache block and to cause a change in state of the cache block).
The interface unit generally implements various customized buffers for different requests that may be generated by the processor core and received from the interconnect. For example, incoming snoop buffers, read request buffers for load misses, write buffers for uncacheable writes, and writeback buffers for writes of evicted cache lines are commonly implemented. Each set of buffers is separate and is designed to store customized information for the corresponding request. The customized buffers may consume large amounts of floor plan space. Additionally, since the buffers are dedicated to different request types, the number of each type of buffer is carefully selected to provide the desired level of performance. Furthermore, at times when a particular request type is prevalent, buffers for other request types may go unused while the prevalent request type is stalled waiting on buffers for that request type to free via completion of earlier requests.